The present invention relates to a process for manufacturing CMOS integrated devices with a reduced gate length.
In particular, the process relates to high voltage fed CMOS integrated devices with gate lengths of less than one micron.
It is known that the punch-through and breakdown of the junction are important limiting factors in reducing the dimensions of devices, since the high doping of the channel required to avoid punch-through can lead to an early breakdown of the junction, due to the increase of the electric field at the junction.
Manufacturing methods are currently known, such as the Lightly Doped Drain (LDD) method, which have the purpose of controlling and reducing the maximum electric field peak. According to these methods, a light implanting of ion species adapted to generate regions with the same type of conductivity as the source and drain regions of the transistor to be manufactured is first performed by means of two successive separate masks. Silicon oxide spacer structures are then generally formed at the sides of the gate regions of the transistors to mask a heavy ion implanting of said source and drain regions. Forming these LDD regions in N-channel transistors and in P-channel transistors, however, is entailing some disadvantages, since in any case it produces a worsening of the electric characteristics of the device, especially of its speed, due to the resistances which are introduced in series to the source and drain regions of the transistors and thus reducing the value of the current flowing through the transistor. This known LDD process furthermore entails a hardly negligible cost increase with respect to conventional CMOS processes, due to the two masks required to produce the individual LDD regions in the two transistors.